1. Description of the Prior Art
The structure of a conventional solid-state imaging device will be described below with reference to the device shown in FIG. 6. Light incident on light-sensitive elements 11 arranged in a two-dimensional array is converted into charge, and a charge equivalent to the quantity of incident light is stored in the light-sensitive elements 11. After the stored charge is read out at a predetermined timing by vertical transfer paths 12, it is sent via the vertical transfer paths 12 and a horizontal transfer path 13 to an output circuit 14, it is converted into a voltage and its current is amplified, then it is output to the outside.
A cross-sectional view of this solid-state imaging device, taken along the line X--X in FIG. 6, is shown in FIG. 7. In FIG. 7, a p.sup.- -well region 23 is formed on an n-type semiconductor substrate 24, and a light-sensitive element 11 and a vertical transfer path 12, together with an element isolation region 25, are formed on the p.sup.- -well region 23. In addition, a read-out electrode 21 is formed on the p.sup.- -well region 23 between the light-sensitive element 11 and the vertical transfer path 12, and a transfer electrode 22 is formed on the vertical transfer path 12. Then a light-proof film 26 that has a hole therein is formed over the electrodes 21 and 22.
Light incident through the hole in the light-proof film 26 is stored in the light-sensitive element 11 as a charge. This stored charge is read out from the vertical transfer path 12 by applying a positive voltage to the read-out electrode 21, then is transferred by a pulse voltage applied to the transfer electrode 22. During this time, a reverse-bias voltage V.sub.sub is applied to the semiconductor substrate 24 by a variable-voltage source 15.
In this solid-state imaging device, the depth of the p.sup.- -well region 23 directly under the light-sensitive element 11 is reduced to X.sub.j, so that any excess charge stored in the light-sensitive element 11 leaks out into the semiconductor substrate 24 via the p.sup.- -well region 23. The distribution of potential along the line A-B of FIG. 7 in this case is shown in FIG. 8. Any charge stored in the light-sensitive element 11 that exceeds the p.sup.- -well's potential barrier voltage V.sub.T (V.sub.T =1V in this example) will leak out into the semiconductor substrate 24. Therefore, if the potential barrier voltage V.sub.T is too large, the maximum amount of charge that can be stored in the light-sensitive element 11 will decrease and the dynamic range of the solid-state imaging device will also decrease. On the other hand, if the potential barrier voltage V.sub.T is too small, excess charge will flow into other light-sensitive elements and the charge transfer paths (the vertical transfer path 12 and horizontal transfer path 13), causing spurious signals. Therefore, the potential barrier voltage V.sub.T must be set to a suitable value. (Problem To Be Solved by the Present Invention)
Even if solid-state imaging devices of the above construction are manufactured by a fixed production process, there will be variations in the resistivity .rho..sub.sub of different semiconductor substrates 24. For this reason, it is well-known that a different reverse-bias voltage must be applied to each solid-state imaging device, to set the potential barrier V.sub.T of the P-well region to be a predetermined valve.
This situation will now be explained with reference to FIG. 9. If, for example, the optimum potential barrier voltage V.sub.T is taken to be 1.0V, a reverse-bias voltage V.sub.sub of 10.0V must be applied to a solid-state imaging device whose semiconductor Substrate has a resistivity of 35 .OMEGA..multidot.cm (see curve g.sub.2).
To ensure this potential barrier voltage V.sub.T of 1.0V in solid-state imaging devices whose semiconductor substrates have resistivities of 27 .OMEGA..multidot.cm or 43 .OMEGA..multidot.cm, corresponding reverse-bias voltage V.sub.sub of 5.0V and 15V must be applied, as shown by curves g.sub.1 and g.sub.3, respectively.
When it comes to manufacturing semiconductor wafers in the high-resistance region, it is generally difficult to control the process to ensure that resistivity is constant, so it is difficult to obtain large numbers of wafers of same resistivity. The conventional remedy is to measure the value of .rho..sub.sub of each substrate and adjust the reverse-bias voltage V.sub.sub in such a way that the potential barrier voltage V.sub.T is always the same. In the examples shown in FIG. 9, reverse-bias voltages V.sub.sub of 5.0V, 10.0V, and 15.0V would have to be applied to the semiconductor substrates whose resistivities .rho..sub.sub are 27 .OMEGA..multidot.cm, 35 .OMEGA..multidot.cm, and 43 .OMEGA..multidot.cm, respectively, in order to obtain a constant potential barrier voltage V.sub.T (=1.0V).
Therefore, this conventional solid-state imaging device has the problem that the reverse-bias voltage V.sub.sub must be adjusted from the outside.